Functieomschrijving

• Developing andmanaging UVM test benches for FPGA-based hardwaredesigns.
• Creating and executing detailed testplans to validate the functionality of FPGAdevices.
• Continuously improving verificationmethodologies and processes to enhance efficiency andquality.
• The design, realization, integration,and test of systems or subsystems for futureproducts.
• Working with a focus on consumerneeds and technological competitiveness, having an outside inapproach for the designs you create & the knowledge you sharewith your team.

Functie-eisen

• Proven experiencewith FPGA design and verification using UVM and SystemVerilog.
• A Bachelor or Master Degree inElectrical Engineering, Informatics, Computer Science orequivalent.
• 5+ years of experience in VHDL andVerilog coding.
• 5+ years of experience inSystem Verilog for verification.
• Familiaritywith industry standards and best practices for FPGAverification.

Arbeidsvoorwaarden
Theright candidate will be provided a challenging and varied positionin a professional, high-tech environment. An appropriate salarybased on your experience and education. Future prospects andexcellent benefits are evident. After a period of secondment andfunctioning properly, you can be contracted by our client. Goodsecondary conditions such as a minimum of 25 holidays and 8,33%holiday allowance. Courses to develop yourself professionally andpersonally via Trinamics Academy. Discount on your healthcare andreferral bonusses and fun activities. Certain pre-employmentscreening checks may be part of this vacancyprocedure.