**ASIC Design Engineer**

Join us at Qblox as we revolutionize the landscape of quantum computing! Our technology is used around the globe by world-class research teams to build a cutting-edge control stack for industrial-scale quantum computers.

Our distributed architecture allows parallel qubit readout, control, and intercommunication, ultimately interacting with physical qubits using high-frequency analog signals. Imagine what it takes to talk to 10,000 qubits with

nanosecond-level synchronization and all-to-all connectivity, and you will understand the massive microarchitectural, design, and verification challenges we face as we transition our logic to dedicated silicon.

We foster a highly collaborative culture. You will take ownership of your projects, influence technical decisions, and work alongside analog/mixed-signal engineers, digital verification specialists, embedded software developers, and physicists.

**Your Role:**

Deconstruct Requirements \& Design: Evaluate system requirements to

architect and implement robust, high-performance digital logic and IP

blocks.

Front-End Flow Ownership: Drive designs through the front-end ASIC

flow, including RTL coding, linting, clock domain crossing (CDC)

analysis, and initial synthesis.

Verification Collaboration: Write block-level self-checking testbenches

and collaborate with the verification team to expand top-level UVM

environments.

Architectural Influence: Propose innovative changes to chip

architecture, power-saving strategies, and team methodologies.

Cross-Functional Sparring: Act as a core technical sparring partner to a

diverse engineering team, continuously pushing for better ways of doing

things.