Job Summary:
We are looking for a Jr. Physical Digital Design Engineer to join our team of Design Engineers in one of our offices in Europe. This role will be on-site, no remote option is available.
The candidate will be responsible for all aspects of physical design and implementation. In this role, you will participate in the efforts of establishing physical design methodologies and flow automation.
Physical Design Engineer will be part of the design development team. The candidate will work on the digital design implementation, and verification of mixed-signal ICs utilizing standard EDA tools. Products to be designed/verified include power management and mixed signal functions.
MPS products include: switching regulators, sensors, motor control, display drivers, audio amplifiers and power management ICs for fast-growing portable and non-portable markets such as broadband modems, notebooks, cell phones, telecom, fiber optics, digital camera, automobile and network equipment.
Essential Functions:
Responsible for physical design, development, & verification of digital / mixed-signal IC’s
Chip & block floorplan/implementation, power/clock distribution, chip assembly, P&R, STA, & LVS/DRC to closure
Work closely with digital/analog design team for physical implementation and custom analog blocks/interface/IP’s
Qualifications:
Requires advanced degree in Elec Engineering/Computer Science or equivalent.
1+ years (preferred) of Physical Digital Design experience.
2+ years (preferred) ASIC design, verification, or related work experience.
Good written/verbal communication English skills and strong teamwork collaboration
Ability to work independently, follow instructions according to design specifications and execute tasks to hit milestones with quality.
Strong knowledge of ASIC development process and digital design techniques.
Experience with programming, scripting and automation languages like Perl/TCL/Unix/Python
Strong technical abilities & understanding in these areas:Verilog/System Verilog coding.Synthesis, CTS, DFT, Extraction, and STA closure across multiple process corners.Multipower domain, signal integrity, & power/IR drop analysis.Linting and CDC requirements.Expertise in both hand-written and tool-driven functional/timing ECO.Physical Design Verification methodology to debug LVS/DRC issues at chip/block levelUser of industry physical tools: Cadence Encounter/Innovus tools(preferred) or Synopsys ICC/ICC2.
Experience with the following is desired:Physical SOC design including uC design(ARM/RISCV)knowledge of power management industry/applicationsI/F: I2C, SPI, USB, PMBUS, etc
Location:
Spain: Barcelona
Netherlands: Enschede /Nijmegen
Portugal: Porto / Lisbon
